1. Field of the Invention
The present invention relates in general to static semiconductor memory devices, such as static RAM, and relates in particular to a memory device which performs stably even if noise is superimposed on the readout control signal.
2. Technical Background of the Invention
Semiconductor memory devices, such as static RAM, are known to utilize internal synchronization method to reduce the power consumption for its operation. The internal synchronization method is a method in which the peripheral circuits of the memory cells are operated, for each change in the address memory, only during a fixed interval of time based on a base pulse signal. This method requires an address change detection circuit ATD which detects a change in the address signal and generates the above mentioned base pulse signal.
Another technique belonging to the internal synchronization method aiming to further reduce the power consumption is known as a pulse drive method. This method is based on pulse driving of the circuits for a fixed time interval, such as word line connected to the memory circuit and the sense amplifier circuit connected to the word line for detecting the data read from the memory cells, in accordance with the base pulse signal generated by the address change detection circuit ATD. This method is referred to as the word line pulse driving method, or the auto power-down method, and is effective for reducing the power consumption of static RAM devices, for example.
FIG. 9 is a schematic circuit diagram for an example of the control circuit 10 using the auto power-down method for devices such as static RAM . This control circuit 10 is provided with pulse width amplifiers 30 and 40. The pulse width amplifier 30 receives the signal via a buffer 102, and outputs signals of pulse widths governed by the delay capacitances C1-C3. The pulse width amplifier 40 receives the signal via a buffer 123, and outputs signals of pulse widths governed by the delay capacitance C4.
The operation of the control circuit 10 for memory readout will be explained with reference to FIG. 10. When there is a change in the externally supplied address signal ADDRESS, then address change detection circuit ATD (not shown) generates a address change signal ATP.sub.1 -ATP.sub.n in accordance with this change. The address change signals ATP.sub.1 -ATP.sub.n are synthesized through the switching elements 1-13 shown in FIG. 9, and inputted into the control circuit 10. The signals are inputted into the pulse width amplifier 30 or 40, through the respective buffer 102 or 123, which generate control signals APD', ATDS' having amplified signal widths as illustrated in FIG. 10.
The control signals APD', ATDS' are used to control various signals which control the overall operations of the static RAM device. For example, the control signals APD', ATDS' along with write enable signals WE', WE and chip select signals CS', CS are inputted into the signal generation circuit shown in FIGS. 4 to 6, and generate signals SAON, DOC, LAT and LAT'. The signal generation circuit shown in FIG. 4 consists of a NAND gate 400 and a buffer 401, and generates a control signal SAON for controlling the ON-OFF actions of sense amplifier circuit 50 (to be explained later) in accordance with the signals WE', ATDS' and CS supplied thereto. The signal generation circuit shown in FIG. 5 consists of buffers 500, 503 and NAND gates 501, 502, and generates a signal DOC. The signal generation circuit shown in FIG. 6 consists of NAND gates 600, 601 and buffers 602, 603, and generate signal LAT, LAT'. The signals DOC, LAT, LAT' are used to control the operation of the data output circuit 60 (to be explained later) shown in FIG. 7. When reading out data from the memory cells, the signals WE' and CS are at the high level "H" while the signals WE, CS' are at the low level "L".
As shown in FIG. 10, when the address signal ADDRESS changes, the control signal APD' changes from the low level (henceforth referred to as the L level) to the high level (henceforth referred to as the H level) while the control signal ATDS' changes from the H level to the L level. Therefore, as shown in FIG. 10, the signals SAON, DOC, LAT' change respectively to the L level, and the signal LAT changes to the H level.
At this time, the sense amplifier circuit 50 (refer to FIG. 7) becomes off state in response to signal SAON, and the P-channel pullup transistors 300, 301 both become on state, causing both output signals SO, SO' from the sense amplifier circuit 50 to be charged to the H level. Here, the clocked inverter 302, 303 supplied with the signals SO, SO' become non-transmitting in response to signal LAT' while the clocked inverter 306, 307 becomes transmitting in response to signal LAT. At this time further because the signal DOC is at the L level, the input signals GP, GN to the data outputting circuit 60 are both set to the L level. Accordingly, the P-channel transistor 350 and the N-channel transistor 351, which constitute the output driver of the data outputting circuit 60, both become off state, and the output terminal OUT becomes high impedance state.
Next, when the above mentioned signal ATDS' changes from the L level to the H level, the signals SAON, DOC and LAT' change from the respective L level to the H level, and the signal LAT changes from the H level to the L level. In this case, the sense amplifier circuit 50 (refer to FIG. 7) becomes on state because the signal SAON is at the H level, and the P-channel pullup transistors 300, 301 both become off state. Therefore, the output signals SO, SO' of the circuit 50 are supplied with the data read out from the memory cells. At this time, the clocked inverter 302, 303 become transmitting, and the clocked inverter 306, 307 become non-transmitting. Here, because the signal DOC is at the H level, one of either the signals GP or GN changes from the L level to the H level in accordance with the data read out from the memory cells. As a result, one of the P-channel transistor 350 or the N-channel transistor 351 becomes on state, and the data from the memory cells are outputted to the output terminal OUT.
Next, after the address signal ADDRESS changes as described above and a given time interval has elapsed, and suppose that the control signal APD' changes from the H level to the L level, and the signal ATDS' changes from the H level to the L level. Accordingly, both control signals SAON, LAT' change from the H level to the L level, and the signal LAT changes from the L level to the H level. When such changes take place, the sense amplifier circuit 50 shown in FIG. 7 becomes off state, and the P-channel pullup transistor 300, 301 becomes on state. Therefore, the output signals SO, SO' are again set to the H level. This means that the power consumption in the sense amplifier circuit 50 is shut down.
Further, in such a condition of the circuit, the clocked inverter 302, 303 are non-transmitting, and the clocked inverter 306, 307 are transmitting. The signal DOC maintains the H level state, the input signals GP, GN in the data outputting circuit 60 remain in latched with the data from the memory cells. Therefore, one of either the P-channel transistor 350 or the N-channel transistor 351 maintains the on state, and the data from the memory cells continue to be outputted to output terminal OUT.
In the memory devices based on the above described conventional auto power-down system, the pulse widths of the control signals APD', ATDS' are determined by the pulse width amplifier 30, 40 (refer to FIG. 9). It is essential that these signals APD', ATDS' be structured such that the memory cell data can be read out correctly even when a false data, for example noise, represented by A' in FIG. 10 is generated during a change in the address signal ADDRESS. To cope with such problems, the control circuit 10 shown in FIG. 9 rapidly switches the control signal APD' from the L level to the H level, by utilizing a number of transistors 108-110 to charge or discharge the nodes of the pulse width amplifier 30. Accordingly, the auto power-down system is rapidly reset to enable repeated reading out of the correct data in accordance with the correct address signal A which follows the false address signal A' caused by the noise. The series of events are illustrated in the latter half of FIG. 10.
However, delay capacitances C1, C2 and C3 are connected to the nodes of the pulse width amplifier 30 for controlling the pulse width of the control signal APD. Therefore, to completely reset the auto power-down mode, it is necessary to completely charge or discharge all of the nodes. In other words, in the node B shown in FIG. 10, it becomes necessary to have a pulse signal of a pulse width which maintains the H level for a specific time interval or duration (designated by T1).
For example, if a noise A' such as the one shown in FIG. 11 appears in the address signal ADDRESS a pulse signal having a pulse width less than T1 is created in the node B (shown in amplifier 30 circuit in FIG. 9). This phenomenon prevents complete charging or discharging of each node in the pulse width amplifier 30, thus generating a control signal APD of a short width. When such a control signal APD having a short pulse width is generated, the control signal ATDS' outputted from the pulse width amplifier 40 (refer to FIG. 9) maintains the L level. In response to such changes in the control signals APD', ATDS', the output signals from each of the signal generating circuits shown in FIGS. 4 to 6, behave as illustrated in FIG. 11. That is, signals SAON, LAT' maintains the L level and the signal LAT maintains the H level, and only the signal DOC becomes the L level signal having a short pulse duration.
In such a condition, the sense amplifier circuit 50 and the data outputting circuit 60 behave as follows. Because the signal SAON becomes the L level, the sense amplifier circuit 50 retains the off state. The signal LAT' and the signal LAT remain at the L level, therefore, the clocked inverter 302, 303 become non-transmitting while the clocked inverter 306, 307 remains transmitting. At this time, the data outputting circuit 60 is inputted with the latched data read out from the memory cells, and one of either the P-channel transistor 350 or the N-channel transistor 351 is retained in the on state. As a result, the data read out from the memory cells are continued to be outputted to the output terminal OUT.
In this condition, if an L level signal is generated only in the signal DOC, the latched data in the signals GP, GN to be inputted to the data outputting circuit 60 are destroyed, and both signals GP, GN are reset to the L level. Therefore, the P-channel transistor 350 and the N-channel transistor 351 both become off state, and this created the problem that ultimately the readout data could not be outputted from the output terminal OUT.
The static semiconductor memory device of the present invention was developed in view of the problems of the existing memory devices as described above, and the objective is to present a highly reliable memory device which is unaffected by external as well as internal noises.